CHIPS High-Throughput High-Resolution X-ray Laminography/Tomography System for Advanced Packaged Semiconductor Devices and Substrates
Archived on March 24, 2026. Original response deadline: . Full description on SAM.gov.
Overview
- Response deadline
- 11:00 AM UTC−04:00
- Posted
- February 24, 2026
- Notice type
- Combined Synopsis/Solicitation
- NAICS
- 334413: Semiconductor and Related Device Manufacturing
- Agency
- Department of CommerceNATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY
Notice details
- Office
- DEPT OF COMMERCE NIST
- Place of performance
- Gaithersburg, Maryland, 20899
- PSC
- 6640: LABORATORY EQUIPMENT AND SUPPLIES
- Last updated
- Aug 21, 2026
Identifiers
- Solicitation number
- 1333ND26QNB030031
- Notice ID
- fcad963625ca4b36b09c834176fbc194
Description
Amendment 0001:
Amendment changes include the following:
- The required response date is extended from February 26, 2026 to March 9, 2026
- No Statement of work change
- Questions and Answers:
Question1: Is there a cleanroom specification?
NIST Response: No. The instrument will be installed in a general purpose lab in the advanced measurement laboratory facility, but not within a cleanroom.
Question 2: Are you flexible on the footprint (size/dimension)
NIST Response: NIST expects the analytical instrument (source, stages, detectors, and shielded enclosure) to fit within the footprint specified by 10.2. Additional space is available in the lab around the instrument for service access, and for support equipment (including chase space for air compressor/dryer if required, and a work area in the lab for control and analysis PCs).
Question 3: Are the devices in JEDEC Trays?
NIST Response: Typically no. NIST requires significant flexibility to load samples that are within the size envelope described by specification 5. Samples will include full wafers, coupons (partial wafers), individual or groups of packaged devices, as well as atypical sample geometries. To meet requirement 5.1, vendors must include 5 sample carriers that are compatible with the automated loading system. Carriers supporting a JEDEC tray is only one possible way to meet that requirement.
See Combined Synopsis Solicitation_1333ND26QNB030031, Attachment 1 - Statement of Work, and Attachment 2 - Applicable Provisions and Clauses attachments for solicitation details.
Award Overview
Contacts
Contracting Officer
Primary Contact
Secondary Contact
Documents
Showing 3 of 3 items
Document | Source | Agency | Posted Date | File Size | Actions | |
|---|---|---|---|---|---|---|
| Combined Synopsis/Solicitation | NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY | Feb 24, 2026 | 54.11 KB | |||
| Combined Synopsis/Solicitation | NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY | Feb 24, 2026 | 52.57 KB | |||
| Combined Synopsis/Solicitation | NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY | Feb 24, 2026 | 70.66 KB |
Lifecycle
1333ND26QNB030031- Combined Synopsis
- 2×Combined SynopsisCurrentFeb 12, 2026
CHIPS High-Throughput High-Resolution X-ray Laminography/Tomography System for Advanced Packaged Semiconductor Devices and Substrates
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Additional Details
Solicitation Number
1333ND26QNB030031
Archive Date
Mar 24, 2026
Office Address
GAITHERSBURG, MD, 20899